1. Field of the Invention
The present invention relates to an electrically rewritable semiconductor memory device. More particularly, it relates to a nonvolatile semiconductor memory device among semiconductor memory devices, and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, an LSI is formed of elements integrated in a two-dimensional plane on a silicon substrate. An increase in storage capacity of a memory absolutely requires downsizing the dimensions of one element (fine pattering) though the fine pattering has been made difficult from the cost and technology in recent years. Fine pattering requires technological improvements in photolithography though the current ArF liquid immersion lithography has a resolution limit, for example, in a rule near 40 nm. Accordingly, much finer pattering requires the introduction of an EUV exposure. The EUV exposure is expensive, however, and not practical in consideration of the cost. Even if fine pattering can be achieved, it is expected to reach physical limits such as the breakdown voltage between elements unless the drive voltage and so forth are scaled. In a word, there is a high possibility of making the device difficult to operate.
In recent years, for the purpose of increasing the degree of memory integration, many semiconductor memory devices including memory cells arranged three-dimensionally have been proposed (see Patent Document 1: JP2003-078044A, Patent Document 2: U.S. Pat. No. 5,599,724, and Patent Document 3: U.S. Pat. No. 5,707,885).
One of the conventional semiconductor memory devices including memory cells arranged three-dimensionally is a semiconductor memory device using SGT (columnar)-structured transistors (see Patent Documents 1-3). The semiconductor memory device using SGT (columnar)-structured transistors includes multiple layers of polysilicon serving as gate electrodes, and a columnar semiconductor portion in the shape of a pillar formed through the multiple layers of polysilicon. The columnar semiconductor portion serves as a channel (body) portion in the transistor. Plural insulated charge storage layers are provided around the columnar semiconductor portion to accumulate charge. The configuration including the polysilicon, the columnar semiconductor portion and the charge storage layer is called a memory string.